Modern digital VLSI circuits commonly operate at about 0.8 V to 1.2 V. However, circuit requirements often call for additional on chip circuits operating at lower voltages and also operating at higher voltages. Example higher voltage circuits are input/output interface circuits with various off-chip system components such as power management switches, analog input circuits conditioning transducer signals, or output analog drive functions for speakers or other actuators. Example lower voltage circuits are high speed, high performance logic circuits.
Typically high speed, low turn on voltage (vt) transistors are added to the baseline complementary metal-oxide-semiconductor (CMOS) flow by adding additional halo patterning and implantation steps and high voltage transistors are added by introducing a second thicker gate oxide to withstand the higher voltage plus additional steps to set the vt. These additional steps add process complexity and cost.
An alternative solution to add high voltage transistors is to use drain extended metal-oxide-semiconductor (DEMOS) transistors that switch high drain voltages with minimum additional process complexity and cost. In a DECMOS transistor a lightly doped extended drain region is formed between the heavily doped drain contact and the transistor channel region. This region fully depletes when a high voltage is applied to the heavily doped drain contact causing a voltage drop between the drain contact and the transistor gate dielectric. With proper design, sufficient voltage may be dropped between the drain contact and the gate dielectric to allow a low gate voltage transistor to be used for the DEMOS transistor. By using a DEMOS transistor a second thicker gate oxide to accommodate the higher voltage is avoided, and additional pattern and implant steps to set the high voltage vt are avoided significantly reducing cost.
One problem with DEMOS transistors is a reduced breakdown voltage due to impact ionization (BVII) and reduced reliability due to channel hot carrier (CHC) generation near the corner of the DEMOS gate which overlies the drain extension. When the DEMOS transistor is turned on, the electric field is maximum (peak electric field) under the drain end of the DEMOS gate. Impact ionization (CHC generation) occurs when the DEMOS current flows through this region of high electric field. One method to improve BVII and CHC reliability is to move the DEMOS current flow away from the drain edge of the DEMOS gate by counter doping the surface of the extended drain where the peak electric field is formed using a shallow implant with opposite dopant type. This increases the resistance at the surface causing the current to follow a lower resistance subsurface path. This reduces current flow through the peak electric field region resulting in reduced CHC generation, improved CHC reliability, and improved BVII. The counter doping method, often called the floating ring method, adds a floating ring photoresist pattern and also a floating ring implant to the process flow thereby increasing cost.
In a typical CMOS process flow at least three additional patterning and implantation steps are used to add a low voltage NMOS transistor, a low voltage PMOS transistor and a DEPMOS transistor. In addition a fourth patterning and implantation step may be used to add the floating ring implant to improve CHC of the DEPMOS transistor.